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taichi-ishitani

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Funding Links: https://github.com/sponsors/taichi-ishitani

GitHub Sponsors Profile

I'm developing OSS for digital circuit engineers. My works are listed below.

RgGen

Code generation tool for CSR (Configuration and Status Register)

TNoC

NoC (Network on Chip) implementation written in SystemVerilog

tvip-axi

UVM based AMBA AXI4 VIP

tvip-apb

UVM based AMBA APB VIP

Featured Works

rggen/rggen

Code generation tool for control and status registers

Language: Ruby - Stars: 373
rggen/rggen-core

RgGen Core Library

Language: Ruby - Stars: 3
rggen/rggen-plugin-template

Project template for RgGen plugin

Language: Ruby - Stars: 3
taichi-ishitani/tnoc

Network on Chip Implementation written in SytemVerilog

Language: SystemVerilog - Stars: 169
taichi-ishitani/tvip-axi

AMBA AXI VIP

Language: SystemVerilog - Stars: 387
taichi-ishitani/tue

Useful UVM extensions

Language: SystemVerilog - Stars: 21