open-logic

Open-Source VHDL Standard Library

Funding Links: https://github.com/sponsors/open-logic

Name: open-logic
Kind: organization
Followers: 64
Following: 0
Total stars: 583
Repositories count: 2
Created at: 2024-06-06T21:33:54.917Z
Updated at: 2025-05-12T08:59:29.548Z
Last synced at: 2025-05-12T08:59:29.548Z

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Open Logic aims to be for FPGA projects what what stdlib is for C/C++ projects. It makes FPGA technology more accessible and makes designs portable between devices.
Open Logic philosophy in a nutshell:

Trustable Code - provide quality metrics (e.g. code coverage) for every element in the documentation
Ease of Use instead of Feature-Creep - Define components with the average user in mind
Clean Documentation (incl. tutorials) - code without good documentation is useless
Pure VHDL - Not using any vendor specific language constructs makes code protable
Vendor Independence - Synthesis attributes for all commonly used tools are provided

Open Logic implements commonly used components in a reusable and vendor/tool-independent way and provide them under a permissive open source license (LGPL modified for FPGA usage, see License.txt), so the code can be used in commercial projects.