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alokerdas

Funding Links: https://github.com/sponsors/alokerdas

Kind: user
Followers: 1
Following: 0
Total stars: 6
Repositories count: 14
Created at: 2023-04-26T06:39:15.405Z
Updated at: 2024-11-27T03:31:21.265Z
Last synced at: 2024-11-27T03:31:21.265Z

GitHub Sponsors Profile

Contributing to open-source EDA tools. Main focus is to develop downstream tools using iVerilog APIs. This can lead to converged tools and methodology in VLSI CAD.

Already developed iLint, an RTL level design rule checker.
Already developed iSynth, a techology independent synthesis tool.
More tools are in pipeline.

Need financial support to accelerate the development.

Current Sponsors: 0
Past Sponsors: 0
Total Sponsors: 0

Featured Works

alokerdas/iLint

This is a tool to check various rules of a digital design written in verilog HDL. This tool uses Icarus Verilog APIs

Language: C++ - Stars: 1

alokerdas/iSynth

Technology independent Verilog synthesis

Language: C++ - Stars: 1

alokerdas/uP16

This is a simple 16 bit ISA based microprocessor.

Language: C++ - Stars: