3vm
Having fun designing chips and sharing the fun with others!
Funding Links: https://github.com/sponsors/3vm
- Name: 3Vikram M
- Location: Bengaluru
- Company: Valsid Tech Pvt. Ltd.
- Kind: user
- Followers: 2
- Following: 0
- Total stars: 3
- Repositories count: 1
- Created at: 2024-05-20T15:29:19.987Z
- Updated at: 2025-03-09T21:55:56.876Z
- Last synced at: 2025-03-09T21:55:56.876Z
GitHub Sponsors Profile
Through my repositories in GitHub, I propose to create many reusable hardware blocks, boosting the productivity of chip designers, students, researchers and makers. The designs are mostly in SystemVerilog and are also used as educational material.
Goals:
Increase chip designer headcount by 100x
Increase every chip designer's productivity by 10x
Will include reusable pure digital logic, mixed signal digital logic + analog model, C/C++ High Level Synthesis cores, verification components.
Overall, increase the chip design output of the industry by 1000x
- Current Sponsors: 0
- Past Sponsors: 0
- Total Sponsors: 0
- Minimum Sponsorship: $1.00
Featured Works
3vm/dsn_verif
Open source design and verification for chipping
Language: SystemVerilog - Stars: 3